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? semiconductor components industries, llc, 2010 december, 2010-- rev. 10 1 publication order number: ncp1203/d ncp1203 pwm current--mode controller for universal off--line supplies featuring standby and short circuit protection housed in soic--8 or pdip--8 package, the ncp1203 represents a major leap toward ultra--compact switchmode power supplies and represents an excellent candidate to replace the uc384x devices. due to its proprietary smartmos ? very high voltage technology, the circuit allows the implementation of complete off--line ac--dc adapters, battery charger and a high--power smps with few external components. with an internal structure operating at a fixed 40 khz, 60 khz or 100 khz switching frequency, the controller features a high--voltage startup fet which ensures a clean and loss--less startup sequence. its current--mode control naturally provides good audio--susceptibility and inherent pulse--by--pulse control. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so--called skip cycle mode and provides improved efficiency at light loads while offering excellent performance in standby conditions. because this occurs at a user adjustable low peak current, no acoustic noise takes place. the ncp1203 also includes an efficient protective circuitry which, in presence of an output over load condition, disables the output pulses while the device enters a safe burst mode, trying to restart. once the default has gone, the device auto--recovers. finally, a temperature shutdown with hysteresis helps building safe and robust power supplies. features ? high--voltage startup current source ? auto--recovery internal output short--circuit protection ? extremely low no--load standby power ? current--mode with adjustable skip--cycle capability ? internal leading edge blanking ? 250 ma peak current capability ? internally fixed frequency at 40 khz, 60 khz and 100 khz ? direct optocoupler connection ? undervoltage lockout at 7.8 v typical ? spice models available for transient and ac analysis ? pin to pin compatible with ncp1200 ? pb--free packages are available applications ? ac--dc adapters for notebooks, etc. ? offline battery chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) marking diagram x = 4, 6, or 1 a = assembly location l = wafer lot y = year w = work week g = pb--free package http://onsemi.com soic--8 d1, d2 suffix case 751 1 8 1 8 1203pxx awl yywwg 1 8 see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information pin connections 1 adj 8 hv 2 fb 3 cs 4 gnd 7 nc 6 v cc 5 drv (top view) 203dx alyw g 1 8 xx = 40, 60, or 100 a = assembly location wl = wafer lot yy = year ww = work week g = pb--free package pdip--8 n suffix case 626
ncp1203 http://onsemi.com 2 figure 1. typical application example emi filter universal input + + ncp1203 + v out aux. adj fb cs gnd hv v cc drv 1 2 3 4 8 7 6 5 * *please refer to the application information section pin function description pin no. pin name function pin description 1 adj adjust the skipping peak current this pin lets you adjust the level at which the cycle skipping process takes place. shorting this pin to ground, permanently disables the skip cycle feature. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. skip cycle occurs when fb falls below vpin1. 3 cs current sense input this pin senses the primary current and routes it to the internal comparator viaanl.e.b. 4 gnd the ic ground -- 5 drv driving pulses the driver?s output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 22 m f. 7 nc -- this unconnected pin ensures adequate creepage distance. 8 hv ensure a clean and lossless startup sequence connected to the high--voltage rail, this pin injects a constant current into the v cc capacitor during the startup sequence.
ncp1203 http://onsemi.com 3 figure 2. internal circuit architecture overload management uvlo high and low internal regulator ? 250 ma hv current source internal v cc 8 7 6 5 hv nc v cc drv 1 2 3 4 q flip--flop dcmax = 80% q 250 ns l.e.b. 40--60--100 khz clock -- + -- + 80 k 20 k 57 k 1v current sense ground fb adj 24 k 25 k + -- v ref reset 1.2 v skip cycle comparator set maximum ratings rating symbol value unit power supply voltage v cc ,drv 16 v power supply voltage on all other pins except pin 5 (drv), pin 6 (v cc ) and pin 8 (hv) -- --0.3to10 v maximum current into all pins except pin 6 (v cc ) and pin 8 (hv) when 10 v esd diodes are activated -- 5.0 ma thermal resistance, junction --to--air, pdip--8 version thermal resistance, juncti on--to--air, soic version thermal resistance, junction--to--case r ja r ja r jc 100 178 57 ? c/w maximum junction temperature tj max 150 ? c temperature shutdown -- 170 ? c hysteresis in shutdown -- 30 ? c operating temperature range t j --40 to +125 ? c storage temperature range t stg --60 to +150 ? c esd capability, human body model, all pins except pin 6 (v cc ) and pin 8 (hv) -- 2.0 kv esd capability, machine model -- 200 v maximumvoltageonpin8(hv)withpin6(v cc ) decoupled to ground with 10 ? m f -- 500 v stresses exceeding maximum ratings may dam age the device. maximum ratings are stres s ratings only. functional operation above the recommended operating conditions is not impli ed. extended exposure to stresses above the re commended operating conditions may affect device reliability.
ncp1203 http://onsemi.com 4 electrical characteristics (for typical values t j =25 ? c, for min/max values t j =0 ? c to +125 ? c, max t j = 150 ? c, v cc = 11 v unless otherwise noted.) characteristic symbol pin min typ max unit supply section (all frequency versions, otherwise noted) turn--on threshold level, v cc going up v cc(on) 6 12.2 12.8 14 v minimum operating voltage after turn--on v cc(min) 6 7.2 7.8 8.4 v v cc decreasing level at which the latchoff phase ends v cclatch 6 -- 4.9 -- v internal ic consumption, no output load on pin 5 icc1 6 -- 750 880 (note 1) m a internal ic consumption, 1.0 nf output load on pin 5, f sw =40khz icc2 6 -- 1.2 1.4 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw =60khz icc2 6 -- 1.4 1.6 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 100 khz icc2 6 -- 2.0 2.2 (note 2) ma internal ic consumption, latch--off phase, v cc =6.0v icc3 6 -- 250 -- m a internal startup current source (pin8biasedat50v) high--voltage current source, v cc =10v ic1 8 3.5 6.0 9.0 ma high--voltage current source, v cc =0 ic2 8 -- 11 -- ma drive output output voltage rise--time @ cl = 1.0 nf, 10--90% of output signal t r 5 -- 67 -- ns output voltage fall--time @ cl = 1.0 nf, 10--90% of output signal t f 5 -- 28 -- ns source resistance r oh 5 27 40 61 sink resistance r ol 5 5.0 10 20 current comparator (pin 5 loaded unless otherwise noted) input bias current @ 1.0 v input level on pin 3 i ib 3 -- 0.02 -- m a maximum internal current setpoint (note 3) i limit 3 0.85 0.92 1.0 v default internal current set point for skip cycle operation i lskip 3 -- 360 -- mv propagation delay from current detection to gate off state t del 3 -- 90 160 ns leading edge blanking duration (note 3) t leb 3 -- 230 -- ns internal oscillator (v cc = 11 v, pin 5 loaded by 1 nf) oscillation frequency, 40 khz version f osc -- 37 42 47 khz oscillation frequency, 60 khz version f osc -- 57 65 73 khz oscillation frequency, 100 khz version f osc -- 90 103 115 khz maximum duty--cycle dmax -- 74 80 87 % feedback section (v cc = 11 v, pin 5 unloaded) internal pullup resistor rup 2 -- 20 -- k pin 3 to current setpoi nt division ratio iratio -- -- 3.3 -- -- skip cycle generation default skip mode level vskip 1 1.0 1.2 1.4 v pin 1 internal output impedance zout 1 -- 22 -- k 1. max value at t j =0 ? c. 2. maximum value @ t j =25 ? c, please see characterization curves. 3. pin 5 loaded by 1 nf.
ncp1203 http://onsemi.com 5 temperature ( ? c) 125 100 75 50 25 0 -- 5 0 150 200 250 300 350 400 i cc @v cc =6v( m a) figure 3. v cc(on) threshold versus temperature figure 4. v cc(min) level versus temperature 8.4 8.2 -- 5 0 0 8.0 7.6 7.2 125 -- 5 0 14.0 13.8 50 12.6 12.4 12.2 100 7.4 25 25 0 125 temperature ( ? c) temperature ( ? c) v cc(min) level (v) v cc(on) threshold (v) 75 13.0 12.8 13.2 13.6 13.4 50 75 100 7.8 figure 5. i c current consumption (no load) versus temperature figure 6. i cc consumption (loaded by 1 nf) versus temperature temperature ( ? c) figure 7. hv current source at v cc =10v versus temperature figure 8. i c consumption at v cc =6v versus temperature temperature ( ? c) temperature ( ? c) 125 100 75 50 25 0 -- 5 0 500 540 580 620 660 700 860 900 i cc , current consumption ( m a) 740 780 820 1.0 1.2 1.4 1.6 1.8 2.0 i cc , 1 nf load consumption (ma) 100 khz 60 khz 40 khz 125 100 75 50 25 0 -- 5 0 4.0 4.5 5.0 5.5 6.0 6.5 7.5 8.0 7.0 hv current source (ma) 100 khz 60 khz --25 --25 -- 2 5 125 100 75 50 25 0 -- 5 0 -- 2 5 1.1 1.3 1.5 1.7 1.9 -- 2 5 40 khz -- 2 5
ncp1203 http://onsemi.com 6 figure 9. drive source resistance versus temperature figure 10. drive sink resistance versus temperature 20 16 -- 5 0 0 14 6 2 125 -- 5 0 60 50 50 25 20 15 100 4 25 25 0 125 temperature ( ? c) temperature ( ? c) drive sink resistance ( ) drive source resistance ( ) 75 30 35 45 40 50 75 100 8 figure 11. maximum current setpoint versus temperature figure 12. frequency versus temperature -- 5 0 0.99 0.97 50 0.89 0.87 0.85 100 25 0 125 temperature ( ? c) temperature ( ? c) maximum current setpoint (v) 75 0.91 0.93 0.95 55 10 12 18 125 100 75 50 25 0 -- 5 0 0 20 40 60 80 100 120 f, frequency (khz) 100 khz 60 khz 40 khz -- 2 5 -- 2 5 -- 2 5 -- 2 5
ncp1203 http://onsemi.com 7 application information introduction the ncp1203 implements a standard current mode architecture where the switch--off time is dictated by the peak current setpoint. this component represents the ideal candidate where low part--count is the key parameter, particularly in low--cost ac--dc adapters, auxiliary supplies etc. due to its high--performance smartmos high--voltage technology, the ncp1203 incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, low--pass filter and startup device. this later point emphasizes the fact that on semiconductor?s ncp1203 does not need an external startup resistance but supplies the startup current directly from the high--voltage rail. on the other hand, more and more applications are requiring low no--load standby power, e.g. for ac--dc adapters, vcrs etc. uc384x series have a lot of difficulty to reduce the switching losses at low power levels. ncp1203 elegantly solves this problem by skipping unwanted switching cycles at a user--adjustable power level. by ensuring that skip cycles take place at low peak current, the device ensures quiet, noise free operation. finally, an auto--recovery output short--circuit protection (ocp) prevents from any lethal thermal runaway in overload conditions. startup sequence when the power supply is first powered from the mains outlet, the internal current source (typically 6.0 ma) is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the v cc(on) level (typically 12.8 v), the current source turns off and no longer wastes any power. at this time, the v cc capacitor only supplies the controller and the auxiliary supply is supposed to take over before v cc collapses below v cc(min) . figure 13 shows the internal arrangement of this structure: figure 13. the current source brings v cc above 12.8 v and then turns off -- + 8 6 4 6maor0 cv cc aux hv 12.8 v/4.9 v once the power supply has started, the v cc shall be constrained below 16 v, which is the maximum rating on pin 6. figure 14 portrays a typical startup sequence with a v cc regulated at 12.5 v: figure 14. a typical startup sequence for the ncp1203 t, time (sec) 3.00 m 8.00 m 13.0 m 18.0 m 23.0 m 13.5 12.5 11.5 10.5 9.5 regulation 12.8 v
ncp1203 http://onsemi.com 8 current--mode operation as the uc384x series, the ncp1203 features a well--known current mode control architecture which provides superior input audio--susceptibility compared to traditional voltage--mode controllers. primary current pulse--by--pulse checking together with a fast over current comparator offers greater security in the event of a difficult fault condition, e.g. a saturating transformer. adjustable skip cycle level by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. this point guarantees a noise--free operation with cheap transformers. skip cycle offers a proven mean to reduce the standby power in no or light loads situations. wide switching--frequency offer four different options are available: 40 khz -- 65 khz ? 100 khz. depending on the application, the designer can pick up the right device to help reducing magnetics or improve the emi signature before reaching the 150 khz starting point. overcurrent protection (ocp) when the auxiliary winding collapses below uvlolow, the controller stops switching and reduces its consumption. it stays in this mode until vcc reaches 4.9 v typical, where the startup source is reactivated and a new startup sequence is attempted. the power supply is thus operated in burst mode and avoids any lethal thermal runaway. when the default goes way, the power supply automatically resumes operation. wide duty--cycle operation wide mains operation requires a large duty--cycle excursion. the ncp1203 can go up to 80% typically. low standby power if smps naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping un--needed switching cycles, the ncp1203 drastically reduces the power wasted during light load conditions. in no--load conditions, the ncp1203 allows the total standby power to easily reach next international energy agency (iea) recommendations. no acoustic noise while operating instead of skipping cycles at high peak currents, the ncp1203 waits until the peak current demand falls below a user--adjustable 1/3 rd of the maximum limit. as a result, cycle skipping can take place without having a singing transformer ? you can thus select cheap magnetic components free of noise problems. external mosfet connection by leaving the external mosfet external to the ic, you can select avalanche proof devices which, in certain cases (e.g. low output powers), let you work without an active clamping network. also, by controlling the mosfet gate signal flow, you have an option to slow down the device commutation, therefore reducing the amount of electromagnetic interference (emi). spice model a dedicated model to run transient cycle--by--cycle simulations is available but also an averaged version to help you closing the loop. ready--to--use templates can be downloaded in orcad?s pspice and intusoft?s from on semiconductor web site, ncp1203 related section. overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true short--circuit protection. a short--circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the auxiliary voltage also decreases because it also operates in flyback and thus duplicates the output voltage, providing the leakage inductance between windings is kept low. to account for this situation and properly protect the power supply, ncp1203 hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty--cycle. the system auto--recovers when the fault condition disappears. during the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. the auxiliary voltage takes place after a few switching cycles and self--supplies the ic. in presence of a short circuit on the output, the auxiliary voltage will go down until it crosses the undervoltage lockout level of typically 7.8 v. when this happens, ncp1203 immediately stops the switching pulses and unbias all unnecessary logical blocks. the overall consumption drops, while keeping the gate grounded, and the v cc slowly falls down. as soon as v cc reaches typically 4.8 v, the startup source turns--on again and a new startup sequence occurs, bringing v cc toward 12.8 v as an attempt to restart. if the default has gone, then the power supply normally restarts. if not, a new p rotective burst is initiated, shielding the smps from any runaway. figure 15, on the following page, portrays the typical operating signals in short circuit.
ncp1203 http://onsemi.com 9 figure 15. typical waveforms in short circuit conditions 7.8 v 12.8 v 4.9 v v cc driving pulses calculating the v cc capacitor the v cc capacitor can be calculated knowing the ic consumption as soon as v cc reaches 12.8 v. suppose that a ncp1203p60 is used and drives a mosfet with a 30 nc total gate charge (qg). the total average current is thus made of icc1 (700 m a) plus the driver current, fsw x qg or 1.8 ma. the total current is therefore 2.5 ma. the v available to fully startup the circuit (e.g. never reach the 7.8 v uvlo during power on) is 12.8?7.8 = 5 v. we have a capacitor who then needs to supply the ncp1203 with 2.5 ma during a given time until the auxiliary supply takes over. suppose that this time was measured at around 15 ms. cv cc is calculated using the equation c = ti v or c 7.5 m f . select a 22 m f/16 v and this will fit. skipping cycle mode the ncp1203 automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level (vpin 1), the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the so--called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches (figure 17). suppose we have the following component values: lp, primary inductance = 350 m h fsw , switching frequency = 61 khz ip skip = 600 ma (or 333 mv/rsense) the theoretical power transfer is therefore: 1 2 lpip 2 fsw = 3.8 w if this ic enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 3.8 . 0.1 = 380 mw . to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight: figure 16. skip cycle operation i p(min) = 333 mv/r sense normal current mode operation fb 1v 4.2 v, fb pin open 3.2 v, upper dynamic range when fb is above the skip cycle threshold (1.0 v by default), the peak current cannot exceed 1.0 v/rsense. when the ic enters the skip cycle mode, the peak current cannot go below vpin1/3.3/rsense. the user still has the flexibility to alter this 1.0 v by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. grounding pin 1 permanently invalidates the skip cycle operation. however, given the extremely low standby power the controller can reach, the pwm in no--load conditions can quickly enter the minimum t on and still transfer too much power. an instability can take place. we recommend in that case to leave a little bit of skip level to always allow 0% duty cycle.
ncp1203 http://onsemi.com 10 power p1 power p2 power p3 figure 17. output pulses at various power levels (x = 5.0 m s/div) p1 < p2 < p3 figure 18. the skip cycle takes place at low peak currents which guaranties noise--free operation 315.40 882.70 1.450 m 2.017 m 2.585 m 300 m 200 m 100 m 0 max peak current skip cycle current limit we recommend a pin 1 operation between 400 mv and 1.3 v that will fix the skip peak current level between 120 mv/rsense and 390 mv/rsense. non--latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the adj pin 1 level, the output pulses are disabled as long as fb is pulled below pin 1. as soon as fb is relaxed, the ic resumes its operation. figure 19 depicts the application example.
ncp1203 http://onsemi.com 11 figure 19. another way of shutting down the ic without a definitive latch--off state on/off q1 8 7 6 5 1 2 3 4 full latching shutdown other applications require a full latching shutdown, e.g. when an abnormal situation is detected (overtemperature or overvoltage). this feature can easily be implemented through two external transistors wired as a discrete scr. when the v cc level exceeds the zener breakdown voltage, the npn biases the pnp and fires the equivalent scr, permanently bringing down the fb pin. the switching pulses are disabled until the user unplugs the power supply. figure 20. two bipolars ensure a total latch--off of the smps in presence of an ovp laux ncp1203 cv cc rhold 12 k 0.1 m f 10 k 10 k 8 7 6 5 1 2 3 4 ovp rhold ensures that the scr stays on when fired. the bias current flowing through rhold should be small enough to let the v cc ramp up (12.8 v) and down (4.9 v) when the scr is fired. the npn base can also receive a signal from a temperature sensor. typical bipolars can be mmbt2222 and mmbt2907 for the discrete latch. the mmbt3946 features two bipolars npn+pnp in the same package and could also be used. protecting the controller against negative spikes as with any controller built upon a cmos technology, it is the designer?s duty to avoid the presence of negative spikes on sensitive pins. negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered, engendering irremediable damages to the ic if they are a low impedance path is offered between v cc and gnd. if the current sense pin is often the seat of such spurious signals, the high--voltage pin can also be the source of problems in certain circumstances. during the turn--off sequence, e.g. when the user un--plugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and off with a peak current limited by rsense. unfortunately, if the quality coefficient q of the resonating network formed by lp and cbulk is low (e.g. the mosfet rdson + rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. since we are talking about ms pulses, the amount of injected charge (q = i x t) immediately latches the controller which brutally discharges its v cc capacitor. if this v cc capacitor is of sufficient value, its stored energy damages the controller. figure 21 depicts a typical negative shot occurring on the hv pin where the brutal v cc discharge testifies for latchup.
ncp1203 http://onsemi.com 12 figure 21. a negative spike takes place on the bulk capacitor at the switch--off sequence simple and inexpensive cures exist to prevent from internal parasitic scr activation. one of them consists in inserting a resistor in series with the high--voltage pin to keep the negative current to the lowest when the bulk becomes negative (figure 22). please note that the negative spike is clamped to ?2 x vf due to the diode bridge. also, the power dissipation of this resistor is extremely small since it only heats up during the startup sequence. another option (figure 23) consists in wiring a diode from v cc to the bulk capacitor to force v cc to reach uvlolow sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. for security reasons, two diodes can be connected in series. figure 22. a simple resistor in series avoids any latchup in the controller cv cc d3 1n4007 8 7 6 5 1 2 3 4 + cbulk + cv cc rbulk >4.7k 8 7 6 5 1 2 3 4 + cbulk + figure 23. or a diode forces v cc to reach uvlolow sooner
ncp1203 http://onsemi.com 13 ordering information device package shipping ? ncp1203p40g pdip--8 (pb--free) 50 units / rail ncp1203d40r2g soic--8 (pb--free) 2500 units / tape & reel ncp1203p60g pdip--8 (pb--free) 50 units / rail ncp1203d60r2 soic--8 2500 units / tape & reel ncp1203d60r2g soic--8 (pb--free) 2500 units / tape & reel ncp1203p100g pdip--8 (pb--free) 50 units / rail ncp1203d100r2g soic--8 (pb--free) 2500 units / tape & reel ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1203 http://onsemi.com 14 package dimensions soic--8 nb case 751--07 issue aj seating plane 1 4 5 8 n j x45 _ k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751--01 thru 751--06 are obsolete. new standard is 751--07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0808 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 -- x -- -- y -- g m y m 0.25 (0.010) -- z -- y m 0.25 (0.010) z s x s m ____ 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 ? mm inches ? scale 6:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1203 http://onsemi.com 15 package dimensions 8leadpdip case 626--05 issue m 14 5 8 f note 5 d e b l a1 a e3 e a top view c seating plane 0.010 ca side view end view end view note 3 dim min nom max inches a -- -- -- -- -- -- -- -- 0 . 2 1 0 a1 0.015 -------- -------- b 0.014 0.018 0.022 c 0.008 0.010 0.014 d 0.355 0.365 0.400 d1 0.005 -------- -------- e 0.100 bsc e 0.300 0.310 0.325 l 0.115 0.130 0.150 -- -- -- -- -- -- -- -- 5 . 3 3 0 . 3 8 -- -- -- -- -- -- -- -- 0.35 0.46 0.56 0.20 0.25 0.36 9.02 9.27 10.02 0 . 1 3 -- -- -- -- -- -- -- -- 2.54 bsc 7.62 7.87 8.26 2.92 3.30 3.81 min nom max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimension e is measured with the leads re- strained parallel at width e2. 4. dimension e1 does not include mold flash. 5. rounded corners optional. e1 0.240 0.250 0.280 6.10 6.35 7.11 e2 e3 -- -- -- -- -- -- -- -- 0 . 4 3 0 -- -- -- -- -- -- -- -- 1 0 . 9 2 0.300 bsc 7.62 bsc e1 d1 m 8x e/2 e2 c on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s technical experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant int o the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the scillc product could create a situation where personal inj ury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthoriz ed application, buyer shall indemnify and hold scillc and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, cos ts, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, an y claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the p art. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable copyright la ws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 ncp1203/d smartmos is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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